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更新:2024-03-28
Lead Product Engineer (DDR IP)
面议
南京浦口区  | 3-5年  | 硕士  | 社招
已结束
职位详情
年终奖金
五险一金
餐费补贴
领导好
发展空间大
公司规模大
管理规范
上市公司
带薪年假
定期体检
Job Summary:

Join a growing and dynamic IP team and help lead the development of best in class digital and mixed signal IP products.  This is a tremendous opportunity to work with an experienced team focusing on development of high-performance IP related to DDR DDR4/DDR5/LPDDR4/LPDDR5.

The role will be a key member of technical staff in an organization responsible for IP activities including but not limited to Pre-sales engagement with potential customers, Pre-Silicon integration and Post silicon bring-up and test support for the customers.

This candidate will be the primary interface between customer and CDNS R&D team. Candidate should possess strong communication skills with ability to manage multiple priorities on day-to-day basis. Ownership of tasks, ability to collaborate with remote teams located worldwide and clear communication of status, must have attributes in this role.

 

Primary Responsibilities:

Responsible for supporting integration / customization / post silicon bring up of CDNS DDR IP subsystems.
Analyze and resolve complex subsystem application or implementation issues and provide professional guidance to customers.
Support DDR PHY and controller SOC integration reviews, and integration questions.
Perform RTL and gate level simulations to verify functionality.
Assist customers with gate level simulations and timing closure.
Participate in development of CDNS documentations and checklists for customers.
Support post silicon bringup and deployment activities by our customers.
Enhance customer experience by providing prompt updates to customers.

Position Requirements:             

M.S. Electrical/Computer Engineering (or similar degree) with 3+ years of overall experience
Experience working with DDR4/5, LPDDR4/5 IP.
Verilog RTL design and gate level verification experience.
Synthesis and STA experience, back-end experience is a plus.
Familiarity with industry standard DFT flows and test methodologies.
Familiarity with package and board design.
Ability to read schematics and participate in SI/PI reviews for customer board/package implementation.



Preferred Qualifications

Experience with DDR PHY and DSP based architectures.

其他信息
语言要求:英语
工作地址
南京-浦口区新城总部大厦
公司介绍
1992年Cadence公司进入中国大陆市场,迄今已拥有大量的集成电路(IC)及系统级设计客户群体。在过去的三十多年里,Cadence公司在中国不断发展壮大,建立了北京、上海、深圳、南京分公司,并于2008年将亚太总部设立在上海,Cadence中国现拥有员工超过1000人。北京研发中心和上海研发中心主要承担美国总部EDA软件研发任务,此外还在南京设立专门的设计IP研发团队,力争提供给用户更加完美的设计工具和全流程服务。Cadence在中国拥有强大的技术支持团队,提供从系统软硬件仿真验证、数字前端和后端及低功耗设计、数模混合RF前端仿真与DFM以及后端物理验证、系统分析和多物理场仿真、计算流体力学、SiP封装以及PCB设计等技术支持。
工商信息
以下信息来自
企业类型
有限责任公司(外商投资企业法人独资)
经营状态
存续
行业类型
科技推广和应用服务业
成立日期
2011年08月09日
注册地址
中国(上海)自由贸易试验区东育路221弄1号5-9层(实际楼层为4-8层)
统一社会信用代码
91310115580579548F
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