职位详情
Job Summary
As a member of the core backend team, you will be responsible for the physical implementation (from netlist to tapeout) of a highly complex SOC utilizing state of the art process technology
Description
1.Work with FE team to understand chip architecture and drive physical aspects early in design cycle.
2.Design automation; Construct, Guide, Modify, Enhance Timing tools and flows.
3.Top level floorplan, partition floorpan, P&R, timing and physical sign off.
Key Qualification
1.The ideal candidate will have a minimum of 3 years of physical design experience, with recent successful tapeouts in deep sub-micron technology.
2.Expert in top /block level P&R implementation, including floorplanning, clock & power distribution, timing closure, physical & electrical verification.
3.Experienced in industry standard tools, understand their capabilities and underlying algorithms.
4.Strong communication skills.
5.Familiar with sub-micro Synthesis, PR and power sign off tool is a plus.
6.Experience with DDR, PCIE is a plus.
7.Strong scripting abilities in Python are needed; TCL or Makefile is a plus.
8.Experience in methodology of Technology under 16nm is a plus.
9.Experience in large - scale chip design is a plus.
Education
BS/MS CE or EE.
其他信息
行业要求:全部行业
工作地址
北京-海淀区北京中科寒武纪科技有限公司北京市海淀区知春路七号致真大厦D座