职责描述：
1. Implement DFT structures (internal-scan (stuck-at, at-speed), JTAG, MBIST, hard IP testing structure) in block/chip level design.
2. Generate, simulate and debug the block/chip level test bench.
3. Interface with back-end physical design team to complete timing closure for test related logic
4. Interface with operation team to debug production test-vectors for wafer test and final test
任职要求：
1.M.S. or B.S. degree in EE or equivalent
2.3+ years work experience in DFT design
3. Familiar with chip level DFT design and verification
4. Attend the training course of Functional Safety
5. Logical thinking and sensitive to the problem with good self-study and problem shooting ability
6. Good communication capability and teamwork spirit

其他信息

行业要求：全部行业