职责描述：

• RTL Coding, including block design, top level design, Lower power design, CPF/UPF design.
• Verify design and debug in RTL-level, gate-level and PG gate level.
• Simulation, Design constraints, Coding Style checking, Cross clock domain checking, Synthesis and timing closure,
• Bug analysis and fixing, Formal check.
• Area, Power, FIT estimation/measure, DFT related, ATE support.
• Deliver design/verification/application documents/SPEC.
• Work closely with algorithm engineer to develop/debug new IP/product.
• Work closely with verification/system/Firmware engineer to verify/validate new IP/product.
• Work closely with architecture and FW to define function of blocks.
• Work closely with architecture and FW to settle down soc level, subsystem, block level FW/HW partition, architecture.
• Be able to learn new knowledge.

任职要求：Requirements:
• Experience in Verilog code design and verification.
• Experience in Unix/Linux OS, and scripting language like perl.
• Experience in ASIC frontend flow and related tools (synthesis, formal, STA and DFT tools).
• Experience in Lower power design and verification with UPF/CPF.
• Good understand on circuit design and timing constraint for synthesis/STA.
• Familiar with C, UVM.
• Familiar with formal check, DFT related, ATE related.
• Strong issue solving ability.
• Strong communication skills, with the ability to convey complex technical concepts to other design peers in verbal and written form.
• A high level of self-motivation, the ability to be a self-starter, good attitude and high responsibility.
• Good written, verbal and presentation communication skills, good team work.
• BS with 8+ years work experience or MS with 5+ years work experience.

The below knowledge and skills are plus:
• Demonstrated SSD controller design experience.
• Complicated SOC design experience.
• Expertise on PCIe and NVMe.
• Expertise on DDR and NAND flash.