职位详情
五险一金
年终奖金
住房补贴
领导好
发展空间大
公司规模大
Responsibilities:
- Participate in DFT feature and architecture definition for complex SOC
- Implement DFT logic/circuit including SCAN, Boundary SCAN, MBIST, Analog Macro test logic
- Generate DFT related timing constraints and support timing closure with backend engineer
- DFT test patterns generation, simulation and debug
Qualifications:
- 2+ years experience in DFT design and verification, test pattern development
- Good knowledge of Scan/ATPG, MBIST and boundary scan and other DFT techniques
- Understanding of DFT architecture such as JTAG, Scan compression Techniques, scan chain insertion and verification, analog testing
- Good knowledge of digital SoC design, including STA, verification and RTL coding
- Proficient in hardware description languages such as Verilog
- Strong commitment to schedule and work quality, good team player
- Good English hearing, speaking, reading and writing capabilities
其他信息
行业要求：全部行业
公司介绍
NXP Semiconductors N.V. (NASDAQ: NXPI) brings together bright minds to create breakthrough technologies that make the connected world better, safer and more secure. As a world *******in secure connectivity solutions for embedded applications, NXP is pushing boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets while delivering solutions that advance a more sustainable future. Built on more than 60 years of combined experience and expertise, the company has approximately 31,000 employees in more than 30 countries and posted revenue of $13.21 billion in 2022. Find out more at ************
恩智浦半导体NXP Semiconductors N.V.（Nasdaq: NXPI）汇集英才，共同创造突破性技术，为更智慧安全的互联世界保驾护航。作为全球**的嵌入式应用安全连接解决方案提供商，恩智浦不断寻求汽车、工业物联网、移动设备和通信基础设施市场的突破，同时不断推出解决方案，助力实现可持续发展的未来。恩智浦拥有超过60年的专业技术及经验，在全球30多个国家设有业务机构，员工达31,000人，2022年全年营业收入132.1亿美元。更多信息请登录**********************
