Responsibilities:
• Work with algorithm team and design engineers to fully understand the assigned functional blocks and develop test plan based on the architecture of ASIC.
• Implement test benches and test cases with UVM methodology.
• Responsible for functional verification on block and full chip level, work with design engineers to achieve design objectives.
• Conduct and maintain verification methodologies such as regression, code coverage and functional coverage analysis.
• Participate in RTL and post-layout gate level simulation with SDF back-annotation.
• Participate in pre-silicon validation using FPGA platform, and post-silicon bring up on EVB.
Requirements:
• MSEE and related with 1-5 years relevant verification experience.
• Familiar with System Verilog and advance UVM/VMM/OVM methodologies.
• Knowledge of OOPs concepts and C++.
• Verification experience with mixed signal design and C/SystemC/C++ co-simulation environment is a plus.
• Domain knowledge in networking ASICs, such as Ethernet PCS/PMA layer or higher layer in IP stack is definitely a plus.
• Experienced in one or more scripting languages, such as Perl, TCL, Python and Makefile.
• Good English communication and documentation skill.
职位描述：
1、与算法团队和设计工程师合作，根据芯片架构和设计方案制定验证计划；
2、完成基于UVM方法学的验证平台开发， 以及testcase编写；
3、执行模块级和芯片级验证、回归测试，以及代码覆盖率和功能覆盖率分析；
4、参与后仿验证及芯片测试。
岗位要求：
1、电子、通信、计算机等相关专业， 硕士学历，具有1-5年相关验证经验；
2、熟悉Verilog、System Verilog语言，UVM/VMM/OVM验证方法学；
3、具有混合信号设计和C/System C／C++协同仿真验证经验优先考虑；
4、熟悉以太网PCS/PMA层或IP协议栈优先考虑；
5、熟悉一种或多种脚本语言，如Perl、TCL、Python或Makefile；
6、良好的中英文书面和口头表达能力。
福利待遇:
1、固定工资、年底奖金、额外绩效奖金、期权激励、晋升培训；
2、五险一金，补充商业医疗保险，享有国家规定的法定节假日及带薪年假（年假、婚假、产假、病假）等待遇；
3、周末双休、弹性工作时间；
4、定期团建、下午茶歇、过节福利、团队聚餐、生日蛋糕、定期体检；
5、公司提供免费单身公寓，环境好；
6、办公环境舒适，地铁10号线直达，附近多个公交站点，交通十分便利。
注：办公地址：浦口。

其他信息
语言要求：英语
行业要求：全部行业
所属部门：技术中心