职责描述：
The qualified candidate will be offered to join an experienced and highly successful team, for a reasonable base pay, plus a generous grant of stock options that has the potential of great financial reward soon.

The candidate should be a self-driven, easy to work with, team player, willing to work hard toward the success of a startup company, and help solve all the problems necessary to reach that goal.

The job is responsible for the design verification of various parts of a complex state-of-the-art SOC, from testplanning, to testbench and test development, simulation and debugging, regression, documentation, coverage measurement, all the way to tapeout and post-silicon validation.

Duties will also involve mentoring and ramping up new engineers in the same discipline.
任职要求：
● Can communicate effectively in written and spoken English
● RTL design architecture for ASIC, specifications, and testplanning
● RTL and testbench development using UVM methodology and SystemVerilog
● RTL and testbench simulation and debug using a waveform debugger
● Using commercial tools such as Synopsys and Cadence.
● Device modeling and Verification IPs, such as DDR, NAND flash, NVMe, PCIe and AXI
● Strong in programming languages such as C/C++/Perl/Python
● Bug tracking, regression and coverage measurement methodology
● Random testing
● Experience with emulator and FPGA is helpful
● Documentation and tracking for specs, plans, status and bugs
● Mentoring and coaching new or junior engineers for tools, architecture, processes and schedule.

其他信息


所属部门：设计部门